A semiconductor IC has a large number of circuit devices with complex interconnections. The placement of the circuit devices and the routing of the interconnections between the circuit devices of the IC may be facilitated with an Electronic Design Automation (EDA) tool, which allows an enormous flexibility in design and optimization of the IC. EDA technologies typically run on an operating system in conjunction with a microprocessor-based computer system or other programmable control system.
The placement and routing of the circuit devices presents unique design challenges. Placing the circuit devices at relatively greater distances from each other, or “under-packing,” may waste wirelength, as longer wires have to be used to interconnect the circuit devices at greater distances from one another. The longer wires consume higher dynamic power to carry the signals, compared to shorter wires that consume less power. Furthermore, longer wires may have a higher resistance, and therefore, a higher voltage has to used for signal transmission. In addition, packing the circuit devices loosely may also increase the footprint of the circuit to allow for the greater distances between the circuit distances.
On the other hand, placing the circuit devices closer together, or “over-packing,” may increase congestion in the circuit. For the closely packed circuit devices, a large number of interconnecting wires may have to be fitted in smaller routing channels. The number of wires in the routing channels may be limited by physical constraints, such as keeping the wires at a certain distance to not cause a short. Over-packing may cause overloading of the routing channels and may cause congestion.
What is therefore needed is a system that can reduce the wirelength of the IC by packing the circuit devices closer together but also avoids congestion. In other words, what is needed is a system that can determine optimal placement and routing of circuit devices which reduces wirelength and congestion at the same time.